Six animated chapters — technology evolution, working principle, comparison, advantages, economic value and the challenges ahead — turn beginners into experts in one sitting.
DRAM scaled on a 2D plane for four decades. When lithography shrink hit its cost wall, the industry turned to the third dimension: stack dies, drill TSVs, and connect them vertically.
2D lithography shrink drove density for 40+ years.
Below ~1x nm, shrink cost and capacitance/crosstalk explode.
Through-Silicon Vias connect dies vertically with ultra-short paths.
Multiple thin DRAM dies stack on a logic base die.
Tenfold bandwidth with lower per-bit power.
A 3D DRAM module is like a skyscraper of memory. Several thin DRAM dies are stacked vertically and drilled with thousands of TSVs. Micro-bumps or hybrid bonding connect each layer, and a logic die at the bottom drives all of them.
Illustrative normalized values — each card notes its own reference. Energy per bit follows AMD's public claim: hybrid-bonded 3D DRAM uses roughly 1/17 the energy of HBM; d-Matrix's vertical-bonding demo measured 0.37 pJ/bit vs ~2-3 pJ/bit for HBM4 (order-of-magnitude, not exact).
In AI training, memory bandwidth and power dominate cost. HBM and 3D DRAM move data in parallel through thousands of vertical channels instead of long planar buses.
AMD — the company behind 3D V-Cache — says hybrid-bonded 3D DRAM cuts energy per bit by roughly 17× versus conventional HBM stacks. That is the strongest industry signal yet that 3D DRAM is the next big memory path.
The silicon industry now agrees the HBM route to AI compute growth is stalling: converting wafers into HBM stacks yields far less usable capacity than generic DRAM. Attention is shifting to SRAM decode, LPDDR PIM, CXL pooling and 3D DRAM — with 3D DRAM seen as the most promising.
Stacked beside the XPU — DRAM dies stack vertically and talk through TSVs; the whole stack sits next to the compute die, with the PHY in the bottom base die shuttling data sideways to the XPU.
Every layer-to-layer link uses microbumps: tiny solder balls that leave gaps, need underfill, add parasitic resistance and trap heat.
Stacked directly above the XPU — no PHY bottleneck: the PHY layer disappears, and dies connect with hybrid bonding (Cu-Cu, no bumps).
Hybrid bonding: wafer surfaces are polished to atomic flatness, dielectric layers fuse at room temperature at molecular level, then heat treatment makes copper atoms expand and fuse directly together.
Four structural wins come directly from stacking instead of shrinking.
8x single-die capacity — 128Gb vs 16Gb (NEO 230-layer PoC).
5x+ the bandwidth of HBM-class systems (d-Matrix 100 TB/s vs HBM4 18 TB/s).
~80% lower energy per bit vs HBM — 0.37 pJ vs 2-3 pJ (d-Matrix).
Reuses mature 3D NAND lines — high-yield, low-cost (NEO, illustrative).
Stacking amortizes wafer area: instead of paying a huge premium for extreme lithography, you build capacity upward and reap economies of scale.
Training clusters starve for bandwidth; 3D DRAM closes the gap at lower cost than HBM-only designs.
More capacity per rack and lower energy per bit cut total cost of ownership.
Stacked memory fits small footprints with the power efficiency mobile SoCs demand.
17× energy efficiency is exciting — but the road to mass production is full of hard problems. Three hurdles dominate the discussion.
The heat-treatment step of hybrid bonding can push DRAM refresh rates down: high temperature degrades the cell's ability to hold charge.
Bonding surfaces must be polished to atomic flatness — even a nanometer-scale particle can break the bond and kill the die.
The process demands an extremely strict cleanroom environment; any contamination risks yield and drives up cost.